The GPIO Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The GPIO IIP can be implemented in any technology.
The GPIO IIP core supports the standard protocol of GPIO specifications. GPIO IIP also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, AXI, Wishbone, VCI, Avalon, PLB, Wishbone or custom buses.
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