The MIL STD 1553 IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The MIL STD 1553 IIP can be implemented in any technology.
The MIL STD 1553 IIP core supports the MIL STD 1553B specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AXI, AHB, APB, OCP, Wishbone, VCI, Avalon PLB, Tilelink or custom buses.
The MIL STD 1553 IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The MIL STD 1553 IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.
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