The IEEE 1588 - 2019 IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The PTP 1588v IIP can be implemented in any technology.
The IEEE 1588 - 2019(PTP) IIP core supports the Ethernet protocol standard of IEEE standard specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses .
The IEEE 1588 – 2019 IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The IEEE 1588 IIP is validated using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.
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