The eMMC Device IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The eMMC Device IIP can be implemented in any technology.
The eMMC Device IIP core supports the JESD84-B50 specification ad supporting standards. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, AXI, OCP, Wishbone, VCI, Avalon, PLB, Tilelink, Wishbone or custom buses.
The eMMC Device IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The eMMC Device IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.
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