The Ethernet 10M/100M/1G MAC IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The Ethernet 10M/100M/1G MAC IIP can be implemented in any technology.
The Ethernet 10M/100M/1G MAC IIP core supports the Ethernet protocol standard of IEEE 802.3.2018 specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses .
The Ethernet 10M/100M/1G MAC IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Ethernet 10M/100M/1G MAC IIP is validated using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.
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